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rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. ad7226 lc 2 mos quad 8-bit d/a converter functional block diagram control logic dac a dac b dac c dac d latch a latch b latch c latch d a b c d msb data (8-bit) lsb wr a1 a0 v ss agnd agnd v ref v dd v out a v out b v out c v out d d a t a b u s ad7226 general description the ad7226 contains four 8-bit voltage-output digital-to- analog converters, with output buffer amplifiers and interface logic on a single monolithic chip. no external trims are required to achieve full specified performance for the part. separate on-chip latches are provided for each of the four d/a converters. data is transferred into one of these data latches through a common 8-bit ttl/cmos (5 v) compatible input port. control inputs a0 and a1 determine which dac is loaded when wr goes low. the control logic is speed-compat- ible with most 8-bit microprocessors. each d/a converter includes an output buffer amplifier capable of driving up to 5 ma of output current. the amplifiers?offsets are laser-trimmed during manufacture, thereby eliminating any requirement for offset nulling. specified performance is guaranteed for input reference voltages from 2 v to 12.5 v with dual supplies. the part is also specified for single supply operation at a reference of 10 v. the ad7226 is fabricated in an all ion-implanted high speed linear compatible cmos (lc 2 mos) process, which has been specifically developed to allow high speed digital logic circuits and precision analog circuits to be integrated on the same chip. product highlights 1. dac-to-dac matching since all four dacs are fabricated on the same chip at the same time, precise matching and tracking between the dacs is inherent. 2. single-supply operation the voltage mode configuration of the dacs allows the ad7226 to be operated from a single power supply rail. 3. microprocessor compatibility the ad7226 has a common 8-bit data bus with individual dac latches, providing a versatile control architecture for simple interface to microprocessors. all latch enable signals are level triggered. 4. small size combining four dacs and four op amps plus interface logic into a 20-pin package allows a dramatic reduction in board space requirements and offers increased reliability in systems using multiple converters. its pinout is aimed at optimizing board layout with all the analog inputs and outputs at one end of the package and all the digital inputs at the other. features four 8-bit dacs with output amplifiers skinny 20-lead dip, soic, ssop, and plcc packages microprocessor-compatible ttl/cmos-compatible no user trims extended temperature range operation single supply operation possible applications process control automatic test equipment automatic calibration of large system parameters, e.g., gain/offset
rev. c ? ad7226?pecifications (v dd = 11.4 v to 16.5 v, v ss = ? v 10%, agnd = dgnd = 0 v; v ref = +2 v to (v dd ?4 v) 1 , unless otherwise noted. all specifications t min to t max unless otherwise noted.) dual supply parameter k, b versions 2 unit conditions/comments static performance resolution 8 bits total unadjusted error 1lsb maxv dd = 15 v 5%, v ref = 10 v relative accuracy 0.5 lsb max differential nonlinearity 1l sb max guaranteed monotonic full-scale error 0.5 lsb max full-scale temperature coefficient 20 ppm/ c typ v dd = 14 v to 16.5 v, v ref = +10 v zero code error 20 mv max zero code error temperature coefficient 50 m v/ c typ reference input voltage range 2 to (v dd ?4) v min to v max input resistance 2 k w min input capacitance 3 50 pf mi n occurs when each dac is loaded with all 0s. 200 pf ma x occurs when each dac is loaded with all 1s. digital inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input leakage current 1 m a max v in = 0 v or v dd input capacitance 8 pf max input coding binary dynamic performance voltage output slew rate 4 2.5 v/ m s min voltage output settling time 4 4 m s max v ref = 10 v; settling time to 1/2 lsb digital crosstalk 10 nv secs typ minimum load resistance 2 k w min v out = 10 v power supplies v dd range 11.4/16.5 v min/v max for specified performance i dd 13 ma max outputs unloaded; v in = v inl or v inh i ss 11 ma max outputs unloaded; v in = v inl or v inh switching characteristics 4, 5 address to write setup time, t as 0ns min address to write hold time, t ah 0ns min data valid to write setup time, t ds 50 ns min data valid to write hold time, t dh 0ns min write pulsewidth, t wr 50 ns min notes 1 maximum possible reference voltage. 2 temperature ranges are as follows: k version: ?0 c to +85 c b version: ?0 c to +85 c 3 guaranteed by design. not production tested. 4 sample tested at 25 c to ensure compliance. 5 switching characteristics apply for single and dual supply operation. specifications subject to change without notice.
rev. c ad7226 ? single supply parameter k, b versions 2 unit conditions/comments static performance resolution 8 bits total unadjusted error 2lsb max differential nonlinearity 1l sb max guaranteed monotonic reference input input resistance 2 k w min input capacitance 3 50 pf mi n occurs when each dac is loaded with all 0s. 200 pf ma x occurs when each dac is loaded with all 1s. digital inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input leakage current 1 m a max v in = 0 v or v dd input capacitance 8 pf max input coding binary dynamic performance voltage output slew rate 4 2v/ m s min voltage output settling time 4 4 m s max settling time to 1/2 lsb digital crosstalk 10 nv secs typ minimum load resistance 2 k w min v out = +10 v power supplies v dd range 14.25/15.75 v min/v max for specified performance i dd 13 ma max outputs unloaded; v in = v inl or v inh notes 1 maximum possible reference voltage. 2 temperature ranges are as follows: k version: ?0 c to +85 c b version: ?0 c to +85 c 3 guaranteed by design. not production tested. 4 sample tested at 25 c to ensure compliance. specifications subject to change without notice. (v dd = 15 v 5%, v ss = agnd = dgnd = o v; v ref = 10 v 1 unless otherwise noted. all specifications t min to t max unless otherwise noted.) absolute maximum ratings 1 v dd to agnd . . . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v, +17 v v dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v, +17 v v ss to agnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? v, v dd v ss to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? v, v dd v dd to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v, +24 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v, v dd digital input voltage to dgnd . . . . . . . ?.3 v, v dd + 0.3 v v ref to agnd . . . . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v, v dd v out to agnd 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ss , v dd power dissipation (any package) to 75 c . . . . . . . . . . 500 mw derates above 75 c by . . . . . . . . . . . . . . . . . . . . . 2.0 mw/ c operating temperature commercial (k version) . . . . . . . . . . . . . . . ?0 c to +85 c industrial (b version) . . . . . . . . . . . . . . . . . ?0 c to +85 c storage temperature . . . . . . . . . . . . . . . . . . . ?5 c to +150 c lead temperature (soldering, 10 secs) . . . . . . . . . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 outputs may be shorted to agnd provided that the power dissipation of the package is not exceeded. typically short circuit current to agnd is 50 ma. ordering guide total 1 temperature unadjusted package model range error option 2 ad7226kn ?0 c to +85 c 1 lsb n-20 ad7226kp ?0 c to +85 c 1 lsb p-20a ad7226kr ?0 c to +85 c 1 lsb rw-20 ad7226bq ?0 c to +85 c 1 lsb q-20 ad7226brs ?0 c to +85 c 1 lsb rs-20 notes 1 dual-supply operation 2 n = plastic dip; p = plastic leaded chip carrier; q = cerdip; rw = soic; rs = ssop caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7226 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
rev. c ? ad7226 pin configurations dip and soic/ssop top view (not to scale) 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 ad7226 v ref agnd dgnd db7 (msb) db6 a0 a1 wr db0(lsb) db5 db4 db3 db2 db1 v ss v out a v out bv out c v out d v dd plcc 3 2 1 20 19 9 10 11 12 13 18 17 16 15 14 4 5 6 7 8 top view (not to scale) v ref a gnd dgnd db7 (msb) db8 ad7226 v dd a0 a1 wr db0(lsb) db5 db4 db3 db2 db1 v ss v out a v out b v out c v out d terminology total unadjusted error this is a comprehensive specification that includes full-scale error, relative accuracy and zero code error. maximum output voltage is v ref ?1 lsb (ideal), where 1 lsb (ideal) is v ref / 256. the lsb size will vary over the v ref range. hence the zero code error will, relative to the lsb size, increase as v ref decreases. accordingly, the total unadjusted error, which includes the zero code error, will also vary in terms of lsb? over the v ref range. as a result, total unadjusted error is specified for a fixed refer- ence voltage of 10 v. relative accuracy relative accuracy or endpoint nonlinearity, is a measure of the maximum deviation from a straight line passing through the endpoints of the dac transfer function. it is measured after allowing for zero and full-scale error and is normally expressed in lsb? or as a percentage of full-scale reading. differential nonlinearity differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb max over the operating temperature range ensures monotonicity. digital crosstalk the glitch impulse transferred to the output of one converter due to a change in the digital input code to another of the con- verters. it is specified in nv secs and is measured at v ref = 0 v. full scale error full-scale error is defined as: measured value ?zero code error ?ideal value
rev. c ad7226 ? circuit information d/a section the ad7226 contains four identical, 8-bit, voltage mode digital-to- analog converters. the output voltages from the converters have the same polarity as the reference voltage allowing single supply opera- tion. a novel dac switch pair arrangement on the ad7226 allows a reference voltage range from 2 v to 12.5 v. each dac consists of a highly stable, thin-film, r-2r ladder and eight high speed nmos, single-pole, double-throw switches. the simplified circuit diagram for one channel is shown in figure 1. note that v ref (pin 4) and agnd (pin 5) are common to all four dacs. rrr 2r 2r 2r 2r 2r db0 db5 db6 db7 v ref agnd shown for all 1s on dac v out figure 1. d/a simplified circuit diagram the input impedance at the v ref pin of the ad7226 is the parallel combination of the four individual dac reference input impedances. it is code dependent and can vary from 2 k w to infinity. the lowest input impedance (i.e., 2 kw ) occurs when all four dacs are loaded with the digital code 01010101. therefore, it is important that the reference presents a low output impedance under changing load conditions. the nodal capacitance at the reference terminals is also code dependent and typically varies from 100 pf to 250 pf. each v out pin can be considered as a digitally programmable voltage source with an output voltage of: vdv outx x ref = (1) where d x is fractional representation of the digital input code and can vary from 0 to 255/256. the source impedance is the output resistance of the buffer amplifier. op amp section each voltage-mode d/a converter output is buffered by a unity gain, noninverting cmos amplifier. this buffer amplifier is capable of developing 10 v across a 2 k w load and can drive capacitive loads of 3300 pf. the output stage of this amplifier consists of a bipolar transistor from the v dd line and a current load to the v ss , the negative supply for the output amplifiers. this output stage is shown in figure 2. the npn transistor supplies the required output current drive (up to 5 ma). the current load consists of nmos transistors which normally act as a constant current sink of 400 m a to v ss , giving each output a current sink capability of approximately 400 m a if required. the ad7226 can be operated single or dual supply resulting in different performance in some parameters from the output amplifiers. in single supply operation (v ss = 0 v = agnd), with the out- put approaching agnd (i.e., digital code approaching all 0s) v dd v ss i/p o/p 400 a figure 2. amplifier output stage the current load ceases to act as a current sink and begins to act as a resistive load of approximately 2 k w to agnd. this occurs as the nmos transistors come out of saturation. this means that, in single supply operation, the sink capability of the ampli- fiers is reduced when the output voltage is at or near agnd. a typical plot of the variation of current sink capability with out- put voltage is shown in figure 3. v out (v) 500 010 2 i sink ( a) 468 400 300 200 100 0 v ss = ?v v ss = 0 v dd = +15v figure 3. variation of i sink with v out if the full sink capability is required with output voltages at or near agnd (= 0 v), then v ss can be brought below 0 v by 5 v and thereby maintain the 400 m a current sink as indicated in figure 3. biasing v ss below 0 v also gives additional headroom in the output amplifier which allows for better zero code error performance on each output. also improved is the slew rate and negative-going settling time of the amplifiers (discussed later). each amplifier offset is laser trimmed during manufacture to eliminate any requirement for offset nulling. digital section the digital inputs of the ad7226 are both ttl and cmos (5 v) compatible from v dd = 11.4 v to 16.5 v. all logic inputs are static protected mos gates with typical input currents of less than 1 na. internal input protection is achieved by an on-chip distributed diode from dgnd to each mos gate. to minimize power supply currents, it is recommended that the digital input voltages be driven as close to the supply rails (v dd and dgnd) as practically possible.
rev. c ? ad7226 interface logic information address lines a0 and a1 select which dac will accept data from the input port. table i shows the selection table for the four dacs with figure 4 showing the input control logic. when the wr signal is low, the input latches of the selected dac are transparent and its output responds to activity on the data bus. the data is latched into the addressed dac latch on the rising edge of wr . while wr is high the analog outputs remain at the value corresponding to the data held in their respective latches. table i. ad7226 truth table ad7226 control inputs ad7226 wr a1 a0 operation hx xn o operation device not selected ll l dac a transparent ll dac a latched ll h dac b transparent lh dac b latched lh l dac c transparent hl dac c latched lh h dac d transparent hh dac d latched l = low state, h = high state, x = don? care a0 a1 w r to latch a to latch b to latch c to latch d figure 4. input control logic t ds t dh t ah t as v inl v inh v inh v inl v dd v dd v dd data address wr 0 0 0 t wr notes 1. all input signal rise and fall times measured from 10% to 90% of v dd . t r = t f = 20ns over v dd range. 2. timing measurement reference level is 3. selected input latch is transparent while wr is low, thus invalid data during this time can cause spurious outputs. v inh + v inl 2 figure 5. write cycle timing diagram
rev. c t ypical performance characteristics?d7226 ? (t a = 25 c, v dd = 15 v, v ss = ? v) input code (decimal equivalent) 2.0 0 16 to ta l unadjusted error (lsbs) 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 v ref = 10v tpc 1. channel-to-channel matching v ref (v) 014 24681012 4 relative accuracy (lsbs) 3 2 1 0 ? ? ? ? ad7226k, b tpc 2. relative accuracy vs. v ref v ref (v) 014 24681012 4 differential nonlinearity (lsbs) 3 2 1 0 ? ? ? ? ad7226k, b tpc 3. differential nonlinearity vs. v ref temperature ( c) 2.0 010 zero code error (lsbs) 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 20 30 40 50 60 70 80 90 100 110 120 130 v out a v out b v out c v out d tpc 4. zero code error vs. temperature
rev. c ? ad7226 specification ranges in order for the dacs to operate to their specifications, the reference voltage must be at least 4 v below the v dd power supply voltage. this voltage differential is required for correct generation of bias voltages for the dac switches. the ad7226 is specified to operate over a v dd range from +12 v 5% to +15 v 10% (i.e., from +11.4 v to +16.5 v) with a v ss of ? v 10%. operation is also specified for a single +15 v 5% v dd supply. applying a v ss of ? v results in im proved zero code error, improved output sink capability with outputs near agnd and improved negative-going settling time. performance is specified over a wide range of reference voltages from 2 v to (v dd ?4 v) with dual supplies. this allows a range of standard reference generators to be used such as the ad780, a 2.5 v band gap reference and the ad584, a precision 10 v reference. note that in order to achieve an output voltage range of 0 v to 10 v a nominal 15 v 5% power supply voltage is required by the ad7226. settling time the output stage of the buffer amplifiers consists of a bipolar npn transistor from the v dd line and a constant current load to v ss . v ss is the negative power supply for the output buffer ampli- fiers. as mentioned in the op amp section, in single supply operation the nmos transistor will come out of saturation as the output voltage approaches agnd and will act as a resistive load of approximately 2 k w to agnd. as a result, the settling time for negative-going signals approaching agnd in single supply opera- tion will be longer than for dual supply operation where the current load of 400 m a is maintained all the way down to agnd. positive-going settling-time is not affected by v ss . the settling-time for the ad7226 is limited by the slew-rate of the output buffer amplifiers. this can be seen from figure 6 which shows the dynamic response for the ad7226 for a full scale change. figures 7a and 7b show expanded settling-time photographs with the output waveforms derived from a differen- tial input to an oscilloscope. figure 7a shows the settling time for a positive-going step and figure 7b shows the settling time for a negative-going output step. data v out figure 6. dynamic response (v ss = ? v) data o/p +1/2 lsb ?/2 lsb figure 7a. positive step settling time (v ss = ? v) data o/p +1/2 lsb ?/2 lsb figure 7b. negative step settling time (v ss = ? v) ground management ac or transient voltages between agnd and dgnd can cause noise at the analog output. this is especially true in micropro- cessor systems where digital noise is prevalent. the simplest method of ensuring that voltages at agnd and dgnd are equal is to tie agnd and dgnd together at the ad7226. in more complex systems where the agnd and dgnd intertie is on the backplane, it is recommended that two diodes be con- nected in inverse parallel between the ad7226 agnd and dgnd pins (in914 or equivalent). unipolar output operation this is the basic mode of operation for each channel of the ad7226, with the output voltage having the same positive polarity as +v ref . the ad7226 can be operated single supply (v ss = agnd) or with positive/negative supplies (see op amp section which outlines the advantages of having negative v ss ). the code table for unipolar output operation is shown in table ii . note that the voltage at v ref must never be negative with respect to dgnd in order to prevent parasitic transistor turn-on. connections for the unipolar output operation are shown in figure 8.
rev. c ad7226 ? dac a dac b dac c dac d msb v ref v dd dgnd agnd v ss v out a wr a1 a0 lsb v out b v out c v out d db7 db0 figure 8. ad7226 unipolar output circuit table ii. unipolar code table dac latch contents msb lsb analog output 1 1 1 1 1 1 1 1 + ? ? ? v ref 255 256 1 0 0 0 0 0 0 1 + ? ? ? v ref 129 256 1 0 0 0 0 0 0 0 + ? ? ? =+ v v ref ref 128 256 2 0 1 1 1 1 1 1 1 + ? ? ? v ref 127 256 0 0 0 0 0 0 0 1 + ? ? ? v ref 1 256 0 0 0 0 0 0 0 0 0 v note lsb v v ref ref : = () () = ? ? ? 2 1 256 8 (2) bipolar output operation each of the dacs of the ad7226 can be individually config- ured to provide bipolar output operation. this is possible using one external amplifier and two resistors per channel. figure 9 shows a circuit used to implement offset binary coding (bipolar operation) with dac a of the ad7226. in this case v r r dv r r v out a ref ref =+ ? ? ? () ? ? ? () 1 2 1 2 1 (3) with r 1 = r 2 vdv out a ref = () 21 ? (4) where d a is a fractional representation of the digital word in latch a. mismatch between r1 and r2 causes gain and offset errors and therefore these resistors must match and track over tempera- ture. once again the ad7226 can be operated in single supply or from positive/negative supplies. table iii shows the digital code versus output voltage relationship for the circuit of figure 9 with r1 = r2. dac a v ref v dd dgnd agnd v ss v out a v out v ref ad7226 * r2 r1 +15v ?5v r1, r2 = 10k 0.1% * digital inputs omitted for clarity figure 9. ad7226 bipolar output circuit table iii. bipolar (offset binary) code table dac latch contents msb lsb analog output 1 1 1 1 1 1 1 1 + ? ? ? v ref 127 128 1 0 0 0 0 0 0 1 + ? ? ? v ref 1 128 1 0 0 0 0 0 0 0 0 v 0 1 1 1 1 1 1 1 ?v ref 1 128 ? ? ? 0 0 0 0 0 0 0 1 ?v ref 127 128 ? ? ? 0 0 0 0 0 0 0 0 ?? vv ref ref 128 128 ? ? ? = agnd bias the ad7226 agnd pin can be biased above system gnd (ad7226 dgnd) to provide an offset ?ero?analog output voltage level. figure 10 shows a circuit configuration to achieve this for channel a of the ad7226. the output voltage, v out a, can be expressed as: vav dv out bias a in =+ () (5) where d a is a fractional representation of the digital input word (0 d 255/256).
rev. c ?0 ad7226 dac a v ref v dd dgnd agnd v ss v out a ad7226 * * digital inputs omitted for clarity 5 v bias figure 10. agnd bias circuit for a given v in , increasing agnd above system gnd will reduce the effective v dd ? ref which must be at least 4 v to ensure specified operation. note that because the agnd pin is common to all four dacs, this method biases up the output voltages of all the dacs in the ad7226. note that v dd and v ss of the ad7226 should be referenced to dgnd. 3-phase sine wave the circuit of figure 11 shows an application of the ad7226 in the generation of 3-phase sine waves which can be used to con- trol small 3-phase motors. the proper codes for synthesizing a full sine wave are stored in eprom, with the required phase- shift of 120 between the three d/a converter outputs being generated in software. data is loaded into the three d/a converters from the sine eprom via the microprocessor or control logic. three loops are generated in software with each d/a converter being loaded from a separate loop. the loops run through the look-up table producing successive triads of sinusoidal values with 120 separation which are loaded to the d/a converters producing three sine wave voltages 120 apart. a complete sine wave cycle is generated by stepping through the full look-up table. if a 256-element sine wave table is used then the resolution of the circuit will be 1.4 (360 /256). figure 13 shows typical resulting waveforms. the sine waves can be smoothed by filter- ing the d/a converter outputs. the fourth d/a converter of the ad7226, dac d, may be used in a feedback configuration to provide a programmable reference voltage for itself and the other three converters. this configuration is shown in figure 11. the relationship of v ref to v in is dependent upon digital code and upon the ratio of r f to r and is given by the formula. v g gd v ref d in = + () + () 1 1 (6) where g = r f / r and d d is a fractional representation of the digital word in latch d. alternatively, for a given v in and resistance ratio, the required value of d d for a given value of v re f can be determined from the expression drr v v r r df in ref f =+ () 1 /? (7) figure 12 shows typical plots of v ref versus digital code for three different values of r f . with v in = 2.5 v and r f = 3 r the peak-to-peak sine wave voltage from the converter outputs will vary between 2.5 v and 10 v over the digital input code range of 0 to 255. digital code (decimal equivalent) 4.0 v in 0 16 v ref 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 3.5 v in 3.0 v in 2.5 v in 2.0 v in 1.5 v in v in r f = 3r r f = 2r r f = r v dd = +15 v v ss = ? v figure 12. variation of v ref with feedback configuration v ref v out a wr a1 a0 v out b v out c v out d ad7226 data bus address bus microprocessor or control logic sine eprom address decode v in r f r figure 11. 3-phase sine wave generation circuit v out a v out b v out c figure 13. 3-phase sine wave output
rev. c ad7226 ?1 staircase window comparator in many test systems, it is important to be able to determine whether some parameter lies within defined limits. the staircase window comparator of figure 14a is a circuit that can be used, for example, to measure the v oh and v ol thresholds of a ttl device under test. upper and lower limits on both v oh and v ol can be programmably set using the ad7226. each adjacent pair of comparators forms a window of programmable size. if v test lies within a window, then the output for that window will be high. with a reference of 2.56 v applied to the v ref input, the minimum window size is 10 mv. v ref v dd agnd v out a v out b v out c v out d v oh (high) v ol (high) v oh (low) v ol (low) v test from d.u.t. 1/4 ca339 10k 5v 10k 5v 5v 5v 10k 10k 5v 10k window 5 window 4 window 3 window 2 window 1 ad7226 figure 14a. logic level measurement v ref agnd v out a v out b v out c v out d window 5 window 4 window 3 window 2 window 1 figure 14b. window structure the circuit can easily be adapted to allow for overlapping of windows as shown in figure 15a. if the three outputs from this circuit are decoded then five different nonoverlapping program- mable windows can again be defined. v ref v dd agnd 5v 10k window 3 v out a v out b v out c v out d v test from d.u.t. 10k 5v 10k 5v window 2 window 1 ad7226 figure 15a. overlapping windows v ref agnd v out a v out b v out c v out d window 3 window 2 window 1 figure 15b. window structure dac a v ref v dd dgnd agnd v ss v out a ad7226 * * digital inputs omitted for clarity +4v ?v +15v 15k 10k figure 16. varying reference signal varying reference signal in some applications, it may be desirable to have a varying signal applied to the reference input of the ad7226. the ad7226 has multiplying capability within upper and lower limits of reference voltage when operated with dual supplies. the upper and lower limits are those required by the ad7226 to achieve its linearity specification. figure 16 shows a sine wave signal applied to the reference input of the ad7226. for input signal frequencies up to 50 khz, the output distortion typically remains less than 0.1%. typical 3 db bandwidth figure is 700 khz.
rev. c ?2 ad7226 offset adjust figure 17 shows how the ad7226 can be used to provide pro- grammable input offset voltage adjustment for the ad544 op amp. each output of the ad7226 can be used to trim the input offset voltage on one ad544. the 620 k w resistor tied to 10 v provides a fixed bias current to one offset node. for symmetri- cal adjustment, this bias current should equal the current in the other offset node with the half-full scale code (i.e., 10000000) on the dac. changing the code on the dac varies the bias current and hence provides offset adjust for the ad544. for example, the input offset voltage on the ad544j, which has a maximum of 2 mv, can be programmably trimmed to 10 m v. dac a v ref v dd dgnd agnd v ss v out a ad7226 * * digital inputs omitted for clarity 620k 500k +15v ?5v 1 4 5 7 +10v figure 17. offset adjust for ad544 wr a1 a0 ad7226 * address/data bus address bus address decode wr en db7 db0 8212 ds2 ale d7 d0 a8 a15 * linear circuitry omitted for clarity 8085a figure 18. ad7226 to 8085a interface wr a1 a0 ad7226 * data bus address bus address decode r/ w en db7 db0 d7 d0 a0 a15 * linear circuitry omitted for clarity en e 6809 figure 19. ad7226 to 6809 interface wr a1 a0 ad7226 * data bus address bus address decode r/ w en db7 db0 d7 d0 a0 a15 * linear circuitry omitted for clarity en 2 6502 figure 20. ad7226 to 6502 interface wr a1 a0 ad7226 * data bus address bus address decode wr en db7 db0 d7 d0 a0 a15 * linear circuitry omitted for clarity z-80 figure 21. ad7226 to z-80 interface
rev. c ad7226 ?3 20-lead plastic dual in-line package [pdip] (n-20) dimensions shown in inches and (millimeters) 20 1 10 11 0.985 (25.02) 0.965 (24.51) 0.945 (24.00) 0.295 (7.49) 0.285 (7.24) 0.275 (6.99) 0.150 (3.81) 0.135 (3.43) 0.120 (3.05) 0.015 (0.38) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) seating plane 0.015 (0.38) min 0.180 (4.57) max 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.100 (2.54) bsc 0.060 (1.52) 0.050 (1.27) 0.045 (1.14) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design compliant to jedec standards mo-095-ae 20-lead ceramic dual in-line package [cerdip] (q-20) dimensions shown in inches and (millimeters) 20 110 11 0.310 (7.87) 0.220 (5.59) pin 1 0.005 (0.13) min 0.098 (2.49) max 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) seating plane 0.200 (5.08) max 1.060 (26.92) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.100 (2.54) bsc 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) controlling dimensions are in inches; millimeters dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design 20-lead shrink small outline package [ssop] (rs-20) dimensions shown in millimeters 20 11 10 1 7.50 7.20 6.90 8.20 7.80 7.40 5.60 5.30 5.00 coplanarity 0.10 0.05 min 1.85 1.75 1.65 0.65 bsc 0.25 0.09 0.95 0.75 0.55 8 4 0 2.00 max 0.38 0.22 seating plane compliant to jedec standards mo-150ae outline dimensions
rev. c ?4 ad7226 outline dimensions 20-lead plastic leaded chip carrier [plcc] (p-20a) dimensions shown in inches and (millimeters) 0.020 (0.50) r bottom view (pins up) 0.040 (1.01) 0.025 (0.64) 0.021 (0.53) 0.013 (0.33) 0.330 (8.38) 0.290 (7.37) 0.032 (0.81) 0.026 (0.66) 0.056 (1.42) 0.042 (1.07) 0.20 (0.51) min 0.120 (3.04) 0.090 (2.29) 3 4 19 18 8 9 14 13 top view (pins down) 0.395 (10.02) 0.385 (9.78) sq 0.356 (9.04) 0.350 (8.89) sq 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07) 0.020 (0.50) r 0.050 (1.27) bsc 0.180 (4.57) 0.165 (4.19) compliant to jedec standards mo-047aa controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design 20-lead standard small outline package [soic] wide body (rw-20) dimensions shown in millimeters and (inches) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-013ac 0.75 (0.0295) 0.25 (0.0098) 20 11 10 1 0.32 (0.0126) 0.23 (0.0091) 8 0 45 1.27 (0.0500) 0.40 (0.0157) seating plane 0.30 (0.0118) 0.10 (0.0039) 0.51 (0.0201) 0.33 (0.0130) 2.65 (0.1043) 2.35 (0.0925) 1.27 (0.0500) bsc 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 13.00 (0.5118) 12.60 (0.4961) coplanarity 0.10
rev. c ad7226 ?5 revision history location page 3/03?ata sheet changed from rev. b to rev. c. title revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3/03?ata sheet changed from rev. a to rev. b. edits to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edits to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 edits to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 edits to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 edits to pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 edits to specifications ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 outline dimensions updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 rs-20 package added . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 updated rs-20 package outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
c00987??/03(c) ?6

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